The present invention relates to a semiconductor memory device and, more particularly, to a MOS (metal oxide semiconductor) type dynamic memory device.
In the MOS type dynamic memory device, as an example of a semiconductor memory device, one transistor/cell type memory device in which a single transistor and a single capacitor are used as a memory cell has dominantly been used aiming at improving a density of integration. In the MOS type dynamic memory device using such memory cells, different signal voltages appearing on a pair of data lines are very small (e.g. about several tens of mV) since the memory cell per se has no amplifying function. To sense such a minute signal, a sense amplifier is used. For accurately sensing the signal voltage by the sense amplifier, prior to the sensing operation by the sense amplifier, the potentials (referred to as initial potentials) on the pair of data lines must be set at the same level.
FIG. 1 shows a circuit construction of a part of a general MOS type dynamic memory device which is related to the present invention.
As shown, a pair of data lines DL and DL are connected to a sense amplifier SA. Coupled with the data lines DL and DL are regeneration circuits RC and RC, a plurality of memory cells (only a couple of memory cells are illustrated, for simplicity), and dummy cells DC and DC. Word lines WL and WL are coupled with the memory cells MC and MC, respectively. The dummy cells DC and DC are also coupled with word lines WLd and WLd, respectively.
The operation of the dynamic memory device as mentioned above will be described referring to FIGS. 2A to 2F. Assume now that a chip enable signal CE (FIG. 2A) is level-shifted from "1" to "0" and the operation phase shifts from an active cycle to a precharge cycle. Through this transient, the word line WL and dummy word line WLd (FIG. 2C) having been activated in the active cycle, the drive pulse .phi..sub.SA (FIG. 2D) to the sense amplifier SA, and the regeneration pulse .phi..sub.REF (FIG. 2E) go to "0" level. Then, the precharge pulse .phi..sub.p (FIG. 2B) goes to "1". When the precharge pulse .phi..sub.p is at "1" level, the data line DL and DL are precharged through transistors T1, T2 and T3 of the sense amplifier SA, while at the same time the data lines DL and DL are short circuited through the transistors T2 and T3. As a result, the data lines DL and DL are set at the same potential (FIG. 2F). In this case, the data lines DL and DL are generally charged up to the maximum voltage V.sub.DD, i.e. the power source voltage, for reducing the stray capacitors associated with the data lines or for ensuring the regeneration of the signal voltages on the data lines which will be performed in the succeeding stage.
To this end, the voltage of the precharge pulse .phi..sub.p corresponding to "1" level is set at least at V.sub.DD +V.sub.TH (V.sub.TH designates the threshold voltage of each of the transistors T2 and T3). The transistors T7 of the dummy cells DC and DC are also turned on, so that the charge stored in the capacitors Csd of the dummy cells DC and DC are discharged, and the potential stored in the capacitors Csd is a power source voltage V.sub.SS ("0" level).
Then, the chip enable pulse CE becomes "1" in level and the operation phase enters the active cycle. In this case, to secure the satisfactory charge into the data lines DL and DL and to ensure the setting of the initial potentials on the data lines to the same value, the precharge pulse .phi..sub.p is kept at "1" level for a while after the chip enable pulse CE becomes "1" in level and the active cycle starts. The precharge pulse .phi..sub.p becomes "0", and then one selected word line WL on the data line DL side (the number of word lines WL in a memory of 16 K bits is 128) and the dummy word line WLd on the opposite data line DL side are "1" in level ("1" level on the word lines WL and WL is set at V.sub.DD+V.sub.TH or more). Subsequently, the charge stored in the capacitors Cs and Csd in the memory cell MC and dummy cell DC which are connected to the selected word lines WL and the dummy word line WLd, respectively, are read out onto the data lines DL and DL, respectively.
At this time, a signal voltage caused by the charge given in accordance with a capacitance ratio of the stray capacitor Cs in the memory cell MC and the stray capacitor C.sub.D associated with the data line DL, appears on the data line DL. In this case, the capacitance of the stray capacitor C.sub.D is considerably larger than that of the capacitor Cs, C.sub.D &gt;&gt;Cs, so that the signal voltage appearing on the data line DL is extremely low. Since the capacitance of the capacitor Csd in the dummy cell DC is approximately 1/2 that of the capacitor Cs in the memory cell MC, there appears on the data line DL a voltage corresponding to an approximately 1/2 that between "1" level and "0" level on the data line DL.
The stored data in the memory cell MC may be detected through the comparison of the magnitudes of those signal voltages on the data lines DL and DL by the cross-connected transistors T4 and T5 in the sense amplifier SA. The sensing operation by the sense amplifier follows. When the drive pulse .phi..sub.SA (FIG. 2D) for the sense amplifier is "1" in level, the transistor T6 is turned on to in turn operate the transistors T4 and T5. As a result, the potential only on the lower potential data line of the data lines DL and DL drops to "0" in level, and the potential on the higher potential data line is kept as it is so that the signal voltage on the higher potential data line is amplified.
The signal voltage on the higher potential data line is actually very low. For this reason, even if the sense amplifier used is very sensitive, the potential on the higher potential data line drops at the operation time. Then, the potential drop on the data leads line is compensated for by the regeneration circuits RC and RC. The connection points Na and Nb in the regeneration circuits RC and RC are charged when the data lines DL and DL are charged in the precharge cycle.
The regeneration circuit RC (or RC), connected to the data line discharged through the operation of the sense amplifier SA by, for example, DC (or DC), is not operated even when the regeneration pulse .phi..sub.REF (FIG. 2E) is "1", because the connection point Na (or Nb) is also discharged. In this situation, the higher potential data line, or the data line not discharged, for example, DL (or DL), is still at higher potential even though the potential on that line is dropped. Therefore, the gate source voltage of a barrier transistor T8b (or T8a) in the regeneration circuit RC (or RC) is the threshold voltage or slightly less, so that the barrier transistor T8b (or T8a) is kept off or substantially off. Accordingly, the connection point Nb (or Na) of the regeneration circuit RC (or RC) is charged up to V.sub.DD +V.sub.TH or more by the capacitor Cb (or Ca) when the regeneration pulse .phi..sub.REF becomes "1" in level. Accordingly, the higher potential data line is charged up to its maximum voltage V.sub.DD through the transistor T9b (or T9a) in the regeneration circuit RC (or RC). In this way, the signal voltage on the higher potential data line is raised to make it easy to sense the data.
The signal voltage difference between the data lines DL and DL when the sense amplifier SA is operated is very small, 20 to 200 mV. Therefore, to correctly sense the data by the sense amplifier, it is necessary to set the potentials (initial potentials) on the data lines DL and DL to substantially the same value before the sensing operation. For example, when a signal voltage difference between the data lines DL and DL is 50 mV, and the setting value difference between the same data lines is 20 mV, the actual signal voltage is reduced almost half.
The initial potential setting is of great significance at the present day, because the signal voltage is reduce a further lower with increase of the memory capacity and with the precharge cycle period (normally 100 .mu.s or so) being shorter with requirement of the high operation speed.
To reliably set the initial potentials on the data lines DL and DL, it might be a satisfactory measure to increase conductances of the transistors T2 and T3 of the sense amplifier SA. This measure, however, is accompanied by increase of the capacitances of the transistors T2 and T3 of the sense amplifier SA against ground. To avoid this, the capacitance of the capacitor for bootstrap in the precharge pulse generation circuit shown in FIG. 3 must be set large. The large capacitor Cp makes it difficult to generate the precharge pulse .phi..sub.p and increases the necessary chip area when the memory device is integrated in fabrication.